Current reuse amplifier

ABSTRACT

A two-stage amplifier of a type of the current re-use configuration is disclosed. The amplifier includes first to third transistors, where the first transistor constitute the first stage, while, the latter two transistors constitute the second stance. The first to third transistors are connected in series between a power supply and ground such that a bias current supplied to the third transistor flows in the second and first transistors. The first transistor in the source thereof is grounded in the DC mode. The second transistor is grounded in the AC mode but floated in the DC mode. The third transistor that outputs an amplified signal is connected in parallel in the AC mode but in series in the DC mode with respect to the second transistor.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to an amplifier for amplifying a radiofrequency (RF) signal, in particular, the invention relates an amplifierwith a type of the current re-use configuration.

2. Related Prior Art

A type of an RF amplifier called as the current re-use configuration hasbeen known and has been disclosed in a Japanese Patent Application laidopen No. JP-2008-035083A, where the current re-use configurationsupplies a bias current for the downstream stage commonly to theupstream stage through the downstream stage. Because the amplifyingstages in the current re-use configuration are connected in seriesbetween the power supply and the ground in the DC mode, such anamplifier may save the bias current. Recent communication system such asa base station for mobile phones requests an amplifier implementedtherein to generate greater and greater output power. However, thecurrent re-use configuration is hard to increase the output powerbecause the bias current in the downstream stage fully flows within theupstream stage.

SUMMARY OF INVENTION

One aspect of the present invention relates to an amplifier thatincludes an upstream stage, a downstream stage, and an intermediate nodebetween the upstream stage and the downstream stage. The amplifierprovides a first transistor in the upstream stage, and second and thirdtransistors and a distributed transmission line in the downstream stage.The first transistor includes a control terminal and two currentterminals, where the control terminal receives an input signal, one ofthe two current terminals is grounded, and another of the two currentterminals is connected to the intermediate node. The second transistorprovides a control terminal and two current terminals, where the controlterminal is coupled with the intermediate node, while, one of the twocurrent terminals is grounded in the AC mode but floated in the DC mode.The third transistor provides a control terminal and two currentterminals, where the control terminal is coupled with the intermediatenode, while, one of the two current terminals is coupled with theanother of the two current terminals of the second transistor throughthe distributed transmission line and another of the two currentterminals of the third transistor outputs an output signal.

Another aspect of the present invention relates also to an amplifier ofa type of a current re-use configuration. The amplifier includes anupstream stage, a downstream stage and a power supply. The upstreamstage, which is grounded in a direct current (DC) mode and analternating current (AC) mode, receives an input signal and outputs anamplified signal. The downstream stage, which is grounded in the AC modebut floated in the DC mode, receives the amplified signal and outputs anoutput signal. The power supply provides a bias current directly to thedownstream stage but indirectly to the upstream stage through thedownstream stage. A feature of the amplifier of the invention is thatthe downstream stage includes two transistors and a distributedtransmission line between the two transistors. One of the twotransistors is connected to the power supply and another of the twotransistors is connected to the upstream stage. The two transistorscommonly receive the amplified signal output from the upstream stage.The transmission line provided between the two transistors may adjustvoltage gains of the two transistors substantially equal to each otherand set phase difference from the amplified signal to the output signalbetween the two transistors substantially equal to each other.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other purposes, aspects and advantages will be betterunderstood from the following detailed description of a preferredembodiment of the invention with reference to the drawings, in which:

FIG. 1 shows a circuit diagram of an amplifier according to embodimentof the present invention;

FIG. 2 shows behaviors of a ratio of the voltage gains of the second andthird transistors, and a difference of phase delays between the secondand third transistors against an electrical length of the distributedtransmission line;

FIG. 3 shows waveforms of the outputs of the amplifier, the secondtransistor, and the third transistor, respectively, as varying power ofthe input signal in the amplifier of the present invention;

FIG. 4 shows waveforms of the outputs of the amplifier, the secondtransistor, and the third transistor, respectively, as varying power ofthe input signal for the circuit without the distributed transmissionline between the second and third transistors according to an examplecomparable to the present invention;

FIG. 5 schematically explains the operation of the second and thirdtransistors in the circuit of the invention and that in the comparableexample for the output power P against the input signal with anamplitude v1;

FIG. 6 is a circuit diagram of an amplifier according to the secondembodiment of the invention;

FIG. 7 is a circuit diagram of an amplifier according to the secondexample comparable to the amplifier of the second embodiment shown inFIG. 6;

FIG. 8 compares saturation power of the amplifier shown in FIG. 6according to the second embodiment of the invention with the amplifiershown in FIG. 7 according to the second comparable example; and

FIG. 9 compares P1 dB characteristics of the amplifier of the secondembodiment shown in FIG. 6 with the amplifier of the second exampleshown in FIG. 7, where the P1 dB means the output power at which thegain of an amplifier decreases by 1 dB from the linear gain; and

FIG. 10 compares IM3 performance of the amplifier of the secondembodiment with that of the amplifier of the second comparable example,where the IM3 means the power of the third order components of theinter-modulation distortion against power of the carrier component.

DESCRIPTION OF EMBODIMENT

Next, an embodiment of the present invention will be described asreferring to accompanying drawings. In the description of the drawings,numerals or symbols same with or similar to each other will refer toelements same with or similar to each other without duplicatingexplanations.

FIG. 1 shows a circuit diagram of an amplifier according to the firstembodiment of the present invention. The amplifier shown in FIG. 1provides transistors, exactly filed effect transistors (FETs), Q₁ to Q₃.The first transistor Q₁ in a source S₁ thereof is grounded through aparallel circuit of a resistor R₁ and a capacitor C₁, where thecapacitor C₁ grounds the source S₁ in the AC mode. The gate G₁ of thefirst transistor Q₁ receives an input signal having frequency componentsin a radio frequency (RF) range from an input terminal IN. The drain D₁is connected to a node N₁ through a transmission line L₀, exactly, adistributed transmission line L₀ both in the AC mode and in the DC mode.The explanation below assumes that a context of “in the AC mode” meansthat two nodes coupled to each other are physically isolated but may beregarded to be a short-circuit for a frequency subject to the amplifier,and another context of “in the DC mode” means that two nodes arephysically connected, which also means that the two nodes may beregarded to be the short circuit at frequencies far lower than thefrequency subject to the amplifier.

For the second transistor Q₂, the source S₂, which is the first currentterminal of a transistor, is grounded through a capacitor C₂ in the ACmode but floated in the DC mode. The source S₂ is also coupled to thenode N₃ through a series circuit of a distributed transmission line L₂and a resistor R₂ in the DC mode, while, the node N₃ is connected to thefirst node N₁ through a distributed transmission line L₁ in the DC mode.The gate G₂ is directly coupled to the third node N₃ in both of the ACand the DC modes. The drain D₂ is also directly coupled to the fourthnode N₄ in both of the AC and the DC modes.

For the third transistor Q₃, the source S₃ thereof is connected to thefourth node N₄ through the distributed transmission line L₃. The gateG₃, which may be called as the control terminal, is coupled with thefirst node N₁ through a capacitor C₃, which means that the gate G₃ isconnected to the first node N₁ in the AC mode but isolated therefrom inthe DC mode. The gate G₃ receives a gate bias V_(GC) through a registerR₃. The drain D₃ thereof, which may be called as the second currentterminal of a transistor, is directly connected to the second node N₂and coupled with the output terminal OUT through a distributedtransmission line L₄, where the output terminal OUT outputs an amplifiedsignal. The output terminal OUT receives a drain bias V_(DD) through adistributed transmission line L₅. One of the terminals of thedistributed transmission line L₅ is bypassed through a capacitor C₄,that is, the capacitor C₄ is, what is called as a bypassing capacitorthat may bypass high frequency components contained in the amplifiedsignal output from the output terminal OUT to the ground. Thus, highfrequency components are suppressed from leaking into the drain biasV_(DD). In the circuit shown in FIG. 1, the distributed transmissionlines, L₀ to L₄, are provided for matching or adjusting impedance viewedat the nodes. The distributed transmission lines, L₀ to L₅, arereplaceable with inductors.

The capacitors, C₁ and C₂, have enough capacitance to ground thesources, S₁ and S₂, in the AC mode but forces the sources, S₁ and S₂, tobe floated in the DC mode. The signal amplified by the first transistorQ₁ is split at the first node N₁, one of which enters the gate G₂ of thesecond transistor Q₂ through the distributed transmission line L₁;while, the other reaches the gate G₃ of the third transistor Q₃ throughthe capacitor C₃. The gate biases of the first and the secondtransistors, Q₁ and Q₂, namely, gate voltages measured from therespective source voltages may be determined by a current flowing in theresistors, R₁ and R₂, and resistance thereof. The gate bias of the thirdtransistor Q₃ may be determined by the gate bias V_(GC) supplied throughthe resistor R₃ and the drain bias of the second transistor Q₂, namely,a drain voltage thereof measured from the source voltage of the secondtransistor Q₂.

The amplifier of the first embodiment has the circuit diagram abovedescribed. Three transistors, Q₁ and Q₃, are connected in series betweenthe drain bias V_(DD) and the ground in the DC mode. That is, the biascurrent supplying from the drain bias V_(DD) flows in the thirdtransistor Q₃ and the second transistor Q₂ from the respective drains,D₃ and D₂, to the sources, S₃ and S₂, and through the distributedtransmission line L₃, then, streams into the first transistor Q₁ throughthe distributed transmission lines, L₀ to L₃. The current stream in theDC mode is denoted by a broken line 50 in FIG. 1. On the other hand, thefirst and second transistors, Q₁ and Q₂, in the sources, S₁ and S₂,thereof are grounded in the AC mode; but the transistors, Q₂ and Q₃,connected in series in the DC mode but in parallel in the AC mode so asto commonly receive the RF signal amplified by the first transistor Q₁from the first node N₁. Also, the outputs of the second and thirdtransistors, Q₂ and Q₃, are superposed at the second node N₂. Thus, theRF signal entering the input terminal IN is amplified by the two-stagearrangement of the three transistors, Q₁ and Q₃, along the solid line 52in the AC mode.

Thus, three transistors, Q₁ to Q₃, may commonly provide the bias currentsupplied from the drain bias V_(DD), which is sometimes called as thecurrent re-use, which may save the power consumption of the amplifier.While, the second amplifying stage of the amplifier provides twotransistors, Q₂ and Q₃, connected in series in the DC mode but inparallel in the AC mode, the amplifier of FIG. 1 may increase the outputpower thereof.

Next, preferable characteristics of the distributed transmission lines,L₂ and L₃, are estimated using respective values exemplarily listedbelow:

Distributed transmission liens, L₀ to L₅, have electrical lengths θ andphysical lengths l of, θ₀=0.5 radian, θ₁=0.2 radian, θ₂=4 θ, θ₃=3 θ,l₄=650 μm, l₅=700 μm, where radian corresponds to a wavelength λg of anRF signal subject to the amplifier, namely λg=2 π radian, which isassumed to be 20 GHz in the present embodiment, and θ is adjusted from 0to 1.5 radian in the embodiment;

Two distributed transmission lines, L₄ and L₅, have physical widths, w₄and w₅, of w₄=30 μm and w₅=30 μm;

Capacitors, C₁ to C₄, have capacitance of C₁=13.5 pF, C₂=7.2 pF, C₃=0.36pF, and C₄=5.4 pF;

Resistors, R₁ to R₃, have resistance of R₁=2.5 Ω, R₂=2.5 Ω, and R₃=2.0 kΩ; and

Biases, V_(DD) and V_(GC) are V_(DD)=7.5 V and V_(GC)=3.6 V,respectively.

The estimation further assumes that the transistors, Q₁ to Q₃, are atype of high electron mobility transistor (HEMT) having a channel layermade of InGaAs and a barrier layer made of AlGaAs, and have sizessubstantially same with each other. The estimation below concentrates onthe electrical lengths of the distributed transmission lines, L₂ and L₃,because these distributed transmission lines, L₂ and L₃, may determinebalance of two transistors, Q₂ and Q₃, connected in series in the DCmode but in parallel in the AC mode, which strongly affect a maximumoutput power of the amplifier.

Responses of voltage signals in the AC mode at the nodes, N₂ and N₄, arecalculated based on the small signal model of the transistors. FIG. 2show a ratio v₂/v₄ of the voltage signals, which corresponds to anefficiency of the third transistor Q₃; and a phase difference ang(v₂/v₄)between two voltage signals, v₂ and v₄, at the respective nodes, N₂ andN₄, as varying the electrical lengths of the second and thirddistributed transmission lines, L₂ and L₃, from 0 to 1.5 radian. Asshown in FIG. 2, the phase difference ang(v₂/v₄) becomes zero (0) atθ=0.2 radian, at which the ratio |v₂/v₄| becomes around 2. Althoughother electrical lengths longer than 0.2 radian set the phase differenceang(v₂/v₄) to be zero, those electrical lengths inevitably result inlonger physical lengths of the distributed transmission lines, L₂ andL₃. Accordingly, the shortest electrical length of 0.2 radian ispractically preferable.

The phase difference ang(v₂/v₄) of zero means that two signals, v₂ andv₄, show phases substantially matching to each other, which also means,when two transistors, Q₂ and Q₃, in the outputs thereof are combined, aloss due to the phase difference may be most effectively eliminated orsuppressed. Also, when the ratio |v2/v4| becomes two (2), twotransistors, Q₂ and Q₃, have a drain-source bias substantially same toeach other. That is, the drain-source voltage v₄ of the secondtransistor Q₂ and that v₂-v₄ of the third transistor Q₃ are equal toeach other; the power P appearing in the second node N₂ becomesP=2×(v₄−v₂)×i, where₁ is an RF current; and two transistors, Q₂ and Q₃,show saturation performance same to each other when the input powerentering the respective gates, G₂ and G₃, increase. On the other hand,when unbalanced states, that is, when the ratio becomes v₂/v₄<<2 orv₂/v₄>>2, one of transistors, Q₂ and Q₃, earlier shows the saturation,which restricts the maximum output power of the amplifier and degradesthe efficiency.

Assuming the electrical length θ=0.2 radian for the distributedtransmission lines, L₂ and L₃, practical waveforms of the signals, v₂and v₄, are evaluated using the large signal model for the transistors,Q₂ and Q₃. FIG. 3 shows the waveforms of the signals, v2, v2-v4, and v4,of the amplifier shown in FIG. 1 as increasing the input power PIN from−15 dBm to 5 dBm. The waveforms for the input power from −15 dBm to 0dBm are triangular. However, voltage signals, v2-v4 and v4 for the inputpower of 5 dBm are deformed from triangles because the transistors, Q₂and Q₃, operate in the saturation region. On the other hand, thewaveform of the signal v₂ for the input power of 5 dBm remains in atriangle. This is because the two distributed transmission lines, L₂ andL₃, may set the phase difference to be zero and the ratio to be 2.

FIG. 4 shows the waveforms of the signals, v2, v2-v4, and v4, for anamplifier without the distributed transmission line L₃ between twotransistors, Q₂ and Q₃; that is, the source S₃ of the third transistorQ₃ is directly connected to the drain D₂ of the second transistor Q₂. Asshown in FIG. 4, the signals, v2, v2-v4, and v4, for the input power of−15 dBm to 5 dBm show triangular waveforms, which means that twotransistors, Q₂ and Q₃, operate in the non-saturated region, namely, inthe linear region, even the input power becomes 5 dBm; but, theamplitude of the signal v2 becomes smaller compared with the amplitudeobtained by the amplifier with the distributed transmission line L₃.When two transistors, Q₂ and Q₃, in the comparable amplifiercorresponding to FIG. 4 operate in the saturation region, the waveformof the signal v2 becomes considerably distorted.

FIG. 5 schematically explains a relation of the output power against asignal v1 at the node N₁, where the signal v1 corresponds to the inputpower PIN. The amplifier without the distributed transmission line L₃operates in a region 54, which is the linear region, at the RF signalv10 corresponding to the input power of 5 dBm. Accordingly, the signal,v2, v2-v4, and v4, show undistorted waveforms as shown in FIG. 4. Whenthe amplifier without the distributed transmission line L₃ operates inthe saturated region 55 in FIG. 5, the RF signals, v2 and v2-v4, showconsiderably distorted waveforms to secure the available output power.Accordingly, such an amplifier without the distributed transmission lineL₃ is inevitably set in the operating point of the transistors, Q₂ andQ₃, to be within the linear region 54.

On the other hand, the amplifier with the distributed transmission lineL₃ operates the two transistors, Q₂ and Q₃, in the region 56 where theoutput power of the amplifier saturates for the input voltage v10corresponding to the input power of 5 dBm; the voltages, v₂-v₄ and v₄,to which the second transistor Q₂ concerns, are distorted as shown inFIG. 3. However, the voltage v4 shows an un-distorted waveform due tothe compensation of the third transistor Q₃ described above and theamplifier may enhance the output power P.

Thus, the amplifier of the embodiment may have two transistors in thesecond stage of the current re-use configuration to enhance the outputpower thereof because the distributed transmission line L₃ maycompensate the phases of the drain output of the two transistors, Q₂ andQ₃, connected in parallel in the AC mode but in series in the DC mode.The distributed transmission line L₃ has an electrical length making thesignal v2 of the drain D₂ of the second transistor Q₂ in the phasethereof matching with the phase of the signal v4 of the drain D₃ of thethird transistor Q₃. Thus, even the two transistors, Q₂ and Q₃, operatein the saturated region; the amplifier is capable of outputting enhancedpower. The distributed transmission line L₃ may have the electricallength there of such that the outputs of the two transistors, Q₂ and Q₃,show a phase difference within ±π/4, or further preferably ±π/8, toenhance the output power without causing distortion. Moreover, thedistributed transmission line L₃ may have the electrical length suchthat the output v₂ of the third transistor becomes that v4 of the thirdtransistor Q₃ multiplied by 1.5 to 2.5, or further preferably 1.8 to2.2.

The distributed transmission line L₂, which is inserted between the gateG₂ and the source S₂ of the second transistor Q₂, may simply adjust thephase difference between two outputs, v2 and v4, and the amplitudethereof. The second resistor R₂ may determine the gate bias, the voltageof the gate G₂ measured from the source S₂, by the DC current flowingtherein. The other distributed transmission line L₁ between two nodes,N₁ and N₃, may also adjust the phase of the signals entering twotransistors, Q₂ and Q₃. The distributed transmission line L₀ is forconverting the impedance at the node N1 viewing the downstream stageinto the impedance at the drain D₁ of the first transistor Q₁ alsoviewing the downstream stage, that is, the distributed transmission lineL₀ converts the impedance at the drain D₁ of the first transistor Q₁viewing the downstream stage into the output impedance of the firsttransistor Q₁.

The source S₂ of the second transistor Q₂ provides only the capacitor C₂against the ground; that is no resistors are connected between thesource S₂ and the ground. This arrangement may ground the source S₂ ofthe second transistor in the AC mode but float in the DC mode. Thus, thecurrent re-use arrangement may be configured.

Second Embodiment

FIG. 6 shows a circuit diagram of another current re-use amplifieraccording to the second embodiment of the present invention. Theamplifier of the second embodiment has features, distinguishable fromthe amplifier of the first embodiment, in that (1) the amplifier of thesecond embodiment divides the second transistor Q₂ in the firstembodiment into two parts symmetrically connected between the first andthe second nodes, N₁ and N₂; (2) a series circuit of a capacitor C₅ andan inductor L₆ is inserted between the input terminal IN and the gate G₁of the first transistor Q₁; and (3) another series circuit of acapacitor C₇ and a distributed transmission line L₁₀ is inserted betweenthe output terminal OUT and the output of the amplifier of the firstembodiment. The gate G₁ of the first transistor is grounded through adistributed transmission line L₇ and also a series circuit of a resistorR₄ and another distributed transmission line L₈. The capacitor C₅ maycut the DC component of the input signal, while, the inductor L₆, andtwo distributed transmission lines, L₇ and L₈, are for matching theinput impedance of the amplifier.

The third transistor Q₃, similar to that of the first embodiment, in thegate G₃ thereof receives the amplified signal from the first node N₁ andbiased by the bias supply V_(GC) through a series circuit of theresistor R₃ and a distributed transmission line L₉, where the highfrequency components contained in the amplified signal v1 and leakingthrough the resistor R₃ may be bypassed by a bypassing capacitor C₆attributed to the bias supply V_(GC). The capacitor C₇ in the outputstage is for cutting the DC component contained in the output signal ofthe amplifier, while, the distributed transmission line L₁₀ is providedfor matching the output impedance of the amplifier with load impedance.Although not explicitly illustrated in figures, the distributedtransmission lines, L₀ to L₁₀, the capacitors, C₁ to C₇, the resistors,R₁ to R₄, and the inductors L₆ are formed on a semiconductor substratecommon to all of those components; that is, the amplifier shown in FIG.6 is formed as a microwave monolithic integrated circuit (MMIC).

Those components appearing in FIG. 6 have respective values of:

Distributed transmission liens, L₀ to L₁₀, have electrical lengths θ,physical lengths l, and physical widths w of, θ₀=0.5 radian, θ₁=0.2radian, θ₂=4 θ, θ₃=3 θ, l₄=650 μm, l₅=700 μm, l₇=330 μm, l₈=200 μm,l₉=760 μm, l₁₀=450 μm, w₄=w₅=30 μm, w₇=w₈=w₉=w₁₀=10 μm, where radiancorresponds to a wavelength 260844-us λg of an RF signal subject to theamplifier, namely λg=2 π radian, which is assumed to be 20 GHz in thepresent embodiment, and θ is adjusted from 0 to 1.5 radian in theembodiment;

Inductor L₆ has a type of spiral inductor with 1.5 turns and a width of20 μm within a total dimension of 120 μm²;

Capacitors, C₁ to C₇, have capacitance of C₁=13.5 pF, C₂=7.2 pF, C₃=0.36pF, C₄=5.4 pF, C₅=0.54 pF, C₅=3.0 pF, and C₇=0.54 pF;

Resistors , R₁ to R₄, have resistance of R₁=R₂=2.5 Ω, R₃=2.0 kΩ, andR₄=50 Ω; Biases, V_(DD) and V_(GC) are V_(DD)=7.5 V and V_(GC)=3.6V,respectively, where the drain bias V_(DD) flows out the current I_(DD)of 50 mA; and

Transistors, Q₁ to Q₃, have the type of high electron mobilitytransistor (HEMT) having a channel layer made of InGaAs, a barrier layermade of AlGaAs, and gate widths of 320 μm, 160 μm, and 320 μm,respectively. Performances of the amplifier of FIG. 6 are evaluated atfrequencies of 18 to 22 GHz.

The performances obtained by the amplifier shown in FIG. 6 is comparedwith those attained in a circuit shown in FIG. 7, where the amplifier inFIG. 7 is a type of also two stage amplifier involving two transistors,Q₁ and Q₂. The circuit elements shown in FIG. 7 have respective valuesof:

Distributed transmission lines, L₀ to L₄ have electrical lengths θ,physical lengths l, and physical widths w of l₀=l₅=400 μm, l₁=1000 μm,l₄=485 μm, w₀=w₁=w₄=w₅=20 μm;

Capacitors C₁ to C₃ have capacitance of C₁=13.5 pF, C₂=1.50 pF, C₄=13.8pF;

Resistors R₁ and R₂ have resistance of R₁=0.65 Ω and R₂=1.50 Ω;

Bias V_(DD) of V_(DD)=5V for providing a current I_(DD) of I_(DD)=50 mA;and

Transistors, Q₁ and Q₂, also have the type of high electron mobilitytransistor (HEMT) having a channel layer made of InGaAs, a barrier layermade of AlGaAs, and gate widths of 320 μm and 320 μm, respectively.Performances of the amplifier of FIG. 6 are evaluated at frequencies of18 to 22 GHz. The circuit shown in FIGS. 6 and 7 are formed as the MMICwith a dimension of 1.6×1.8 mm² common to each other.

FIG. 8 compares saturation power of two amplifiers, where a solid lineindicates the transfer characteristic of the amplifier of FIG. 6, while,a broken line shows the transfer characteristic of the amplifier of FIG.7. The amplifier of FIG. 7 saturates the output power thereof at around15 dBm, while, the amplifier of the second embodiment shown in FIG. 6saturates the output power at about 18 dBm. FIG. 9 compares P1 dBcharacteristics of two amplifiers, where the P1 dB means the outputpower at which the gain of an amplifier decreases by 1 dB from thelinear gain. The amplifier of the second embodiment shown in FIG. 6exceeds the P1 dB of the amplifier of FIG. 7 by about 5 dB in a wholefrequency range of 18 to 22 GHz. Thus, the amplifier of the secondembodiment, even the die size thereof is substantially comparable tothat of the comparable amplifier, may enhance the P1 dB more than 3 dBfrom the comparable amplifier, which is brought by two transistors, Q₂and Q₃, whose outputs are efficiently combined.

FIG. 10 compares IM3 performance between two amplifiers, where the IM3means power of the third order components of the inter-modulationdistortion against power of the carrier component, namely, the power ofthe 0th order component when an amplifier receives two signals whosefrequencies are set close enough, for instance, 10 MHz for the carrierfrequency of 18 to 22 GHz. As shown in FIG. 10, the amplifier of thesecond embodiment may suppress the IM3 more than 15 dB compared withthose attributed to the comparable amplifier of FIG. 7 for the outputpower of 8 to 9 dBm in frequencies from 18 to 22 GHz. Thus, theamplifier of the second embodiment shown in FIG. 6 may also enhance thedistortion performance even in a range of large output power.

In the foregoing detailed description, the amplifier of the type of thecurrent re-use configuration according to the present invention havebeen described with reference to specific exemplary embodiments thereof.It will, however, be evident that various modifications and changes maybe made thereto without departing from the broader spirit and scope ofthe present invention. For instance, the embodiments concentrate on thetransistors, Q₁ to Q₃, of the type of the FET. However, the amplifiersmay implement transistors of the type of bipolar transistor as replacingthe gate, the source, and the drain to the base, the emitter and thecollector of a bipolar transistor, and the dimensions of the FET isreplaceable to the emitter size of the bipolar transistor. Also, thedistributed transmission lines may be replaced to, for instance,inductors, micro-strip lines, coplanar lines, and so on. The signalsubject to the amplifier may have a frequency from 1 to 100 GHz. Thepresent specification and figures are accordingly to be regarded asillustrative rather than restrictive.

The present application claims the benefit of priority of JapanesePatent Application No. 2016-069460, filed on Mar. 30, 2016, which isincorporated herein by reference.

We claim:
 1. An amplifier that includes an upstream stage, a downstreamstage and an intermediate node between the upstream stage and thedownstream stage, the amplifier comprising: a first transistor in theupstream stage, the first transistor including a control terminal andtwo current terminals, the control terminal receiving an input signal,one of the two current terminals being coupled to a ground and anotherof the two current terminals being connected to the intermediate node; asecond transistor in the downstream stage, the second transistorincluding a control terminal and two current terminals, the controlterminal of the second transistor being coupled with the intermediatenode, one of the two current terminals of the second transistor beinggrounded in an AC mode but floated in a DC mode; a third transistor inthe downstream stage, the third transistor including a control terminaland two current terminals, the control terminal of the third transistorbeing coupled with the intermediate node, one of the two currentterminals of the third transistor being coupled with another of the twocurrent terminals of the second transistor and another of the twocurrent terminals of the third transistor outputting an output signal;and a distributed transmission line connected between the another of thetwo current terminals of the second transistor and the one of the twocurrent terminals of the third transistor, wherein the third transistoris connected in series in the DC mode but in parallel in the AC modewith respect to the second transistor.
 2. The amplifier of claim 1,wherein the distributed transmission line has an electrical length thatsubstantially matches a phase of an signal appearing in the another ofthe two current terminals of the third transistor and an signalappearing in the another of the two current terminals of the secondtransistor, and substantially sets an amplitude of the signal appearingin the another of the two current terminals of the third transistor tobe an amplitude of the signal appearing in the another of the twocurrent terminals of the second transistor multiplied with 15 to 2.5. 3.The amplifier of claim 2, wherein the distributed transmission line hasthe electrical length that sets the amplitude of the signal appearing inthe another of the two current terminals of the third transistor to besubstantially twice of the amplitude of the signal appearing in theanother of the two current terminals of the second transistor.
 4. Theamplifier of claim 2, wherein the distributed transmission line has theelectrical length that matches the phase of the signal appearing in theanother of the two current terminals of the second transistor with thephase of the signal appearing in the another of the two currentterminals of the third transistor within a range of ±π/4.
 5. Theamplifier of claim 4, wherein the distributed transmission line has theelectrical length that matches the phase of the signal appearing in theanother of the two current terminals of the second transistor with thephase of the signal appearing in the another of the two currentterminals of the third transistor within a range of ±π/8.
 6. Theamplifier of claim 1, wherein the third transistor in the controlterminal thereof receives an amplified signal output from theintermediate node through a capacitor.
 7. The amplifier of claim 1,further including another distributed transmission line between thecontrol terminal and the one of the two current terminals of the secondtransistor, wherein the another distributed transmission line has anelectrical length that substantially matches a phase of an signalappearing in the another of the two current terminals of the secondtransistor with a phase of an signal appearing in the another of the twocurrent terminals of the third transistor, and sets an amplitude of thesignal appearing in the another of the two current terminals of thethird transistor substantially twice of an amplitude of the signalappearing in the another of the two current terminals of the secondtransistor.
 8. The amplifier of claim 1, further including a powersupply, wherein the first to third transistors are connected in seriesbetween the power supply and ground in the DC mode.
 9. The amplifier ofclaim 8, further including resistors connected between the one of thetwo current terminals of the first transistor and the ground, andbetween the one of the two current terminals of the second transistorand the control terminal of the second transistor, respectively, whereinthe resistors determine gate biases for the first transistor and thesecond transistor by providing a bias current coming from the powersupply thereto.
 10. The amplifier of claim 8, wherein the firsttransistor, the second transistor, and the third transistor have a typeof field effect transistors with gate widths equal to each other.
 11. Anamplifier of a type of a current re-use configuration, comprising: anupstream stage amplifier that receives an input signal and outputs anamplified signal, the upstream stage being grounded in a direct current(DC) mode and an alternating current (AC) mode; a downstream stage thatreceive the amplified signal and outputs an output signal, thedownstream stage being grounded in the AC mode but floated in the DCmode; and a power supply that provides a bias current directly to thedownstream stage but indirectly to the upstream stage through thedownstream stage, wherein the downstream stage includes two transistorsand a distributed transmission line provided between the twotransistors, one of the two transistors being connected to the powersupply and another of the two transistors being connected to theupstream stage, the two transistors commonly receiving the amplifiedsignal output from the upstream stage, the two transistors beingconnected in parallel in the AC mode but in series in the DC mode assandwiching the distributed transmission line therebetween.
 12. Theamplifier of claim 11, wherein the two transistors in the downstreamstage have sizes equal to each other, and wherein the upstream stageincludes a transistor whose size is equal to the sizes of the twotransistors in the downstream stage.
 13. The amplifier of claim 12,wherein the downstream stage further includes an additional transistorconnected in parallel to the one of the two transistors connected to theupstream stage and between another of the two transistor connected tothe power supply and the upstream stage, wherein the additionaltransistor and the one of the two transistors connected to the upstreamstage have sizes equal to each other but a half of a size of the anotherof the two transistors connected to the power supply.
 14. The amplifierof claim 11, wherein the two transistors in the downstream stage show avoltage gains and phase delays substantially equal to each other for theamplified signal coming from the upstream stage to the output signal.15. The amplifier of claim 14, wherein the two transistors in thedownstream stage show the voltage gain and the phase delayssubstantially equal to each other in saturated operating regions.